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INTEGRATED CIRCUITS
DATA SHEET
SAA7283 Terrestrial Digital Sound Decoder (TDSD3)
Preliminary specification File under Integrated Circuits, IC02 1996 Oct 24
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
FEATURES * Single-chip solution including FM and vision filters, analog demodulator and audio switching * Dual standard with automatic selection between PAL system I and BGH including French NICAM L system) * Single low-radiation crystal oscillator for improved EMC * Stereo bitstream audio DACs * Programmable attenuator for matching levels of NICAM and FM audio sources at the output of the device * Full EBU NICAM 728 specification demodulation and decoding * Digital Audio Interface conforming with EBU/IEC 958 * Automatic mute function which switches from NICAM to FM sound when NICAM fails * Compatible with either single-ended or differential DQPSK input signals * Microcomputer controlled via I2C-bus (up to 400 kHz specification). APPLICATIONS * Television receivers * Video cassette recorders. GENERAL DESCRIPTION The SAA7283 is a NICAM receiver solution, developing the well established high quality Terrestrial Digital Sound decoder family from Philips Semiconductors. This innovative IC with analog front-end, offers more impressive features and flexibility with minimum external circuitry. ORDERING INFORMATION TYPE NUMBER SAA7283ZP SAA7283GP PACKAGE NAME SDIP52 QFP64 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7283
The SAA7283 takes, as input, a second IF (intercarrier) Terrestrial TV PAL signal, and performs all the Differential Quadrature Phase Shift Keying (DQPSK) demodulation, digital decoding and digital-to-analog conversion necessary to produce a complete NICAM receiver on a single integrated circuit. The demodulator function includes integrated baseband filters for pulse shaping and unwanted signal rejection, automatic gain control, a low jitter integrated VCO, digital monostable for precise data sampling points and a multi-standard controller to enable automatic locking to either a PAL system I or PAL system BGH input signal (including French NICAM L system). The decoder function performs the descrambling, de-interleaving and reformatting operations required to recover the original data words. The data words are processed through a stereo digital filter, digital de-emphasis network, second order noise shaper and 256 times oversampling Bitstream audio DAC. The SAA7283 then provides a switching output buffer for selecting between FM, NICAM and daisy-chain inputs, and a programmable level attenuation matrix for matching levels of the FM and NICAM audio sources at the output of the device. An additional feature is the inclusion of a Digital Audio Interface (DAI) output IEC 958, which may be disabled if required.
VERSION SOT247-1 SOT319-2
1996 Oct 24
2
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
QUICK REFERENCE DATA SYMBOL VDD IDD fclk Tamb PARAMETER supply voltage supply current clock frequency operating ambient temperature 4.5 - - -20 MIN. 5.0 205 8.192 +25 TYP. 5.5 - - +70 MAX.
SAA7283
UNIT V mA MHz C
1996 Oct 24
3
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
BLOCK DIAGRAM
handbook, full pagewidth
SAA7283
DQPSK 29
MIXREF 28
V
DDF1 V SSF1 COFF CEYE
25 23 30 31 38 39 17 16 36 35 37 41 46 45 42 43 44 54 53 55 CRYSTAL OSCILLATOR
22 QUADRATURE MIXERS, BASEBAND FILTERS AND AGC GAIN STAGE COSINE SINE 21
SOFF SEYE
VDDF2 VSSF2 REMO REMVE I REF VROF VRCF CLKLPF DATAOUT DATAIN XTAL OSC VSSX SDA SCL ADSEL
CARRIER LOOP PHASE DETECTOR AND DATA SLICERS
AGC CONTROLLER
34
PKDET
BITRATE CLOCK RECOVERY
CARRIER LOOP QUADRATURE VCO
27 24
VCONT VCLK
47 50 NICAM 728 DECODER AND DEVICE CONTROLLER 56 57 14 15
PCLK RESET PORT2 MUTE PORM PORA
I2 C
SAA7283GP
DOBM VDDD VSSD 59 DAI DIGITAL FILTER, GAIN, J17 DE-EMPHASIS
49 48 NOISE SHAPER (LEFT CHANNEL) NOISE SHAPER (RIGHT CHANNEL)
VSSDAC
8
BITSTREAM DAC (LEFT CHANNEL) FML EXTL VDDA VSSA VROA VRCA 12 13 61 62 7 63 11 OUTPUT SWITCHES AND BUFFER (LEFT CHANNEL)
(1)
BITSTREAM DAC (RIGHT CHANNEL) 3 2 FMR EXTR
OUTPUT SWITCHES AND BUFFER (RIGHT CHANNEL) 4
MGB464
(1) Represents controller bus.
OPL
OPR
Fig.1 Block diagram (QFP64).
1996 Oct 24
4
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
PINNING PIN SYMBOL SDIP52 MUTE DOBM VDDA VSSA VRCA EXTR FMR OPR n.c. VROA VSSDAC n.c. OPL FML EXTL PORM PORA REMVE REMO SEYE SOFF VSSF1 VCLK VDDF1 VCONT MIXREF DQPSK COFF CEYE PKDET VROF IREF VRCF VDDF2 VSSF2 n.c. CLKLPF 1996 Oct 24 1 2 3 4 5 6 7 8 9 and 10 11 12 13 and 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 QFP64(1) 57 59 61 62 63 2 3 4 9 and 10 7 8 - 11 12 13 14 15 16 17 21 22 23 24 25 27 28 29 30 31 34 35 36 37 38 39 40 41 DESCRIPTION
SAA7283
active LOW mute input; function defined by MUTEDEF (control bit in the I2C-bus register) digital audio interface output that can be 3-stated via I2C-bus analog supply voltage for the audio channels analog ground connection for the audio channels internal audio reference voltage buffer (high-impedance node) external analog input to the right audio channel FM sound input to the right audio channel analog output from the right audio channel not connected; left open-circuit in application internal audio reference voltage buffer output quiet ground connection to DACs not connected; left open-circuit in application analog output from the left audio channel FM sound input to the left audio channel external analog input to the left audio channel active LOW power-on reset mute input; mute cleared by setting silence bit HIGH in I2C-bus (internal pull-up) power-on reset audio select input (internal pull-up) carrier loop-filter connection carrier loop-filter output sine channel eye pattern output for monitoring sine channel offset compensator capacitor output demodulator ground connection 1 carrier loop VCO clock output for monitoring demodulator supply voltage 1 carrier loop VCO control voltage input mixer voltage reference or input when using differential DQPSK signal DQPSK input signal cosine channel offset compensator capacitor output cosine channel eye pattern output for monitoring AGC peak detector storage capacitor output internal demodulator reference voltage buffered output internal demodulator reference current output internal demodulator reference voltage unbuffered output demodulator supply voltage 2 demodulator ground connection 2 not connected; left open-circuit in application clock loop-phase comparator output 5
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
PIN SYMBOL SDIP52 XTAL OSC VSSX DATAIN VSSD PCLK VDDD RESET DATAOUT SCL SDA ADSEL PORT2 Note 1. Pins 1, 5, 6, 18, 19, 20, 26, 32, 33, 51, 52, 58, 60 and 64 are not connected; left open-circuit in application. 40 41 42 43 44 45 46 47 48 49 50 51 52 QFP64(1) 42 43 44 45 48 47 49 50 46 53 54 55 56 DESCRIPTION 8.192 MHz crystal oscillator input 8.192 MHz crystal oscillator output crystal oscillator ground connection serial data input at 728 kbits/s to decoder digital ground connection 728 kHz output clock to DQPSK demodulator digital supply voltage active LOW power-on reset input serial data output at 728 kbits/s from DQPSK demodulator serial clock input for I2C-bus serial data input/output for I2C-bus input that defines I2C-bus address bit 0 (internal pull-up) output that is directly controlled from Port 2 bit in I2C-bus
1996 Oct 24
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
handbook, halfpage
MUTE DOBM VDDA VSSA V RCA
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44 43 42 41 40
PORT2 ADSEL SDA SCL DATAOUT RESET V DDD
EXTR FMR OPR n.c.
PCLK VSSD DATAIN VSSX OSC XTAL CLKLPF n.c. VSSF2 VDDF2 VRCF I REF VROF
n.c. 10 VROA 11 VSSDAC 12 n.c. 13 n.c. 14 OPL 15 FML 16 EXTL 17 PORM 18 PORA 19
SAA7283ZP
39 38 37 36 35 34 33
REMVE 20 REMO 21 SEYE 22 SOFF 23 VSSF1 24 VCLK 25 V DDF1 26
MGB463
32 PKDET 31 30 CEYE COFF
29 DQPSK 28 MIXREF 27 VCONT
Fig.2 Pin configuration for SOT247.
1996 Oct 24
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
56 PORT2
59 DOBM
57 MUTE
63 V RCA
61 V DDA
62 V SSA
ADSEL
54 SDA
64 n.c.
60 n.c.
58 n.c.
n.c. EXTR FMR OPR n.c. n.c. VROA VSSDAC n.c.
52 n.c. 51 n.c. 50 49 48 47 46 45 44 43 RESET VDDD VSSD PCLK DATAOUT DATAIN VSSX OSC XTAL CLKLPF n.c. VSSF2 VDDF2 VRCF I REF VROF PKDET 42 41 40 39 38 37 36 35 34 33 n.c. n.c. 32
MGB462
handbook, full pagewidth
1 2 3 4 5 6 7 8 9
n.c. 10 OPL 11 FML 12 EXTL 13 PORM 14 PORA 15
SAA7283GP
REMVE 16 REMO 17 n.c. 18 n.c. 19 n.c. 20 SEYE 21 SOFF 22 V SSF1 23 24 V DDF1 25 n.c. 26 VCONT 27 MIXREF 28 DQPSK 29 COFF 30 CEYE 31
Fig.3 Pin configuration for SOT319.
1996 Oct 24
VCLK
8
53 SCL
55
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
FUNCTIONAL DESCRIPTION DQPSK demodulation
GAIN CONTROL
SAA7283
NICAM 728 decoding DECODING FUNCTIONS The device performs all decoding functions in accordance with the EBU NICAM 728 specification. After locking to the frame alignment word, the data is de-scrambled by application of the defined pseudo random binary sequence, and the device synchronizes to the periodic frame flag bit C0. The relevant control information and scale factor word is extracted, and with the integrated RAM the data is de-interleaved and the scale factor word is extracted, and expanded to 14 bits. Parity checking on the eleventh bit of each sample word is carried out to reveal any sound sample errors, which if detected are flagged, with the last good sample being held. Automatic muting Enable when AMDIS = LOW. The I2C-bus section has two registers which define an upper and lower limit for the automatic muting function. When the number of errors within a 128 ms period exceeds the number stored in the upper error limit register, then the automatic muting will switch the device output to the FM input, (dependent on the relevant control bits in the I2C-bus) and mute (set to zero) the data input to the filter (in that order). When the error count in a 128 ms period is less than the value stored in the lower error limit register then the data into the filter is uninterrupted, and the device output is switched back to the DAC (dependent on the value of the relevant control bits in the I2C-bus). During the muting operation the open-drain pin MUTE is pulled LOW and the AM bit in the status-byte is set HIGH. Figure 4 shows the dependency of the automatic muting function on error_count, RSSF, C4OV, output state and application mode. The automatic muting function, if enabled, will override user mute via the MUTE pin/bit. When the transmission is DATA format or currently undefined format (C3 = logic 1) the device will automatically switch to the FM inputs regardless of RSSF/C4OV states, and whether the automatic muting function AMDIS is enabled or disabled.
QUADRATURE MIXERS, BASEBAND FILTERS AND AUTOMATIC (AGC)
The DQPSK signal is fed into two differential input mixers, where it is mixed with quadrature phases generated by the carrier-loop quadrature VCO. The quadrature signals modulated onto the NICAM carrier are thus recovered. The mixers can be driven by either a single-ended or differential source. In single-ended mode, the device is driven directly from the sound IF down-converter into the DQPSK input pin, with the MIXREF pin decoupled. In differential mode, the signal is applied between the DQPSK and MIXREF pins. The outputs from the mixers are then fed into a pulse-shaping filter, and FM/vision filter stage which filters out all interference components, including AM carrier for French NICAM L system. The signal from the filtering stages is then fed into the AGC, which ensures that the phase comparator gain remains constant, irrespective of the input signal level. This is important to maintain the stability of Costas loop PLL. AGC CONTROLLER The AGC controller monitors the I and Q channel signals at the input to the carrier loop-phase comparator and generates a reference voltage to set the AGC output level. EYE BUFFER A differential to the single-ended converter provides the baseband signal as an output at the pins CEYE and SEYE for the I and Q channels respectively for eye-height monitoring. BIT RATE CLOCK RECOVERY The I and Q channels are processed using edge detectors and monostables, which generate a signal with a coherent component at the data symbol rate. The outputs from the I and Q channel monostables are each compared with the clock derived from PCLK (364 kHz nominal), the resultant output is used to derive a 3-state control signal used to control two current sources at the CLKLPF output. This error signal is loop filtered and used to control the master clock oscillator. The bit rate clock, PCLK, and symbol clock are derived from the master clock.
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
User mute The error counter is an 8-bit counter which locks at count 255. The counter is reset and its output sent to the I2C-bus every 128 ms. This enables the user to interrogate the number of errors occurring within a 128 ms period. The user can then mute the device by pulling pin MUTE LOW (this function is also provided by the MUTE bit in the I2C-bus) or setting SILENCE bit LOW in I2C-bus to switch input of audio switching buffers to analog ground. Switching buffers The analog switches select between the output of the DACs, the FM input and an external input (EXT). Switching is controlled by bits in the I2C-bus and internal switching function. The external analog inputs should be 1.1 V (RMS) at the input pin, and the output buffers have a voltage drive of 1 V (RMS). NICAM/FM audio level matching Differing audio headroom and alignment levels occur between systems I and BGH, due to the differing systems and broadcast standards. In order to match the NICAM and FM audio output levels without requiring application changes, the device will automatically switch in 4.6 dB attenuation network in the NICAM path for system BGH (this can be disabled by setting the NICLEV bit LOW in I2C-bus). A programmable attenuation network in the FM path only, controlled by bits in I2C-bus, provides additional flexibility for user to match FM and NICAM audio levels (see Table 9). Power-on reset state
SAA7283
Two pins control the initial set-up of the device during power-on reset. PORA (Power-On Reset Audio) When pulled LOW the device will be configured with a 12 dB gain in the oversampling filter and the C4OV bit in the I2C-bus will be set HIGH. This pin when HIGH will configure the device with a 6 dB gain in the oversampling filter and will set C4OV bit in the I2C-bus LOW. PORM (Power-On Reset Mute) This pin when LOW will mute the output of the device at power-on by setting the SILENCE bit in the I2C-bus LOW. To put the device back into a normal mode of operation the SILENCE bit in the I2C-bus must be set HIGH.
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
handbook, full pagewidth
ERROR_COUNT ERROR_MAX
NO
Output is unchanged AM bit = LOW MUTEB pin = HIGH
YES
RSSF = 1
NO
C4ov BIT = 0
NO
Output is unchanged AM bit = LOW MUTEB pin = HIGH
YES
YES
EXT or FM INPUT SWITCHED IN
YES
Output is unchanged AM bit = HIGH (1) MUTEB pin = LOW (1)
When error_count is less than error_min, AM bit = LOW, MUTEB pin = HIGH
NO
SOUND APPLICATION DUAL MONO
YES
DUAL MONO MODE LEFT = RIGHT = M1 SELECTED
NO
Output is unchanged AM bit = LOW MUTEB pin = HIGH
MGB465
NO
YES
Output is switched to FM input AM bit = HIGH MUTEB pin = LOW
When error_count is less than error_min, the output is switched back to NICAM and AM bit = LOW, MUTEB pin = HIGH
(1) Indicating that a mute may occur when user returns to NICAM source.
Fig.4 Flow diagram showing SAA7283 automatic muting function.
1996 Oct 24
11
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
I2C-BUS FORMATS The SAA7283 contains an I2C-bus slave transceiver (up to 400 kHz) permitting a master device to: * Read decoder status information derived from the transmitted digital audio signal
SAA7283
* Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal * Write control codes to select PAL I or PAL BGH configurations * Write control codes to select the available analog switching configurations * Write upper and lower error count limits for automatic muting function * Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software. I2C-bus slave address An address select pin (ADSEL) is provided to allow selection of one of two different slave addresses. The logic state of the ADSEL pin is reflected in the least significant bit of the I2C-bus slave address. Slave address = 101101X (R/W) [ADSEL = 1, address = B6 (R/W) ADSEL = 0, address = B4 (R/W)]. Table 1 SAA7283 slave address BITS A7 1 A6 0 A5 1 A4 1 A3 0 A2 1 A1 selected by ADSEL A0 read/write
The SAA7283 does not acknowledge the I2C-bus general call address. Slave receiver format The slave receiver format is shown in Table 2. Table 2 START Table 3 Slave receiver format slave_addr ACK sub_addr ACK data_byte ACK n-bytes data_byte ACK STOP
Explanation of Table 2 ITEM DESCRIPTION I2C-bus start condition 101101XW logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 logic 0, I2C-bus write to slave receiver I2C-bus acknowledge condition generated by slave receiver sub-address range 00 to 04 (HEX) data byte transmitted to slave receiver I2C-bus stop condition
START Slave_addr X W ACK Sub_addr Data_byte STOP
The sub-address is auto-incremented by the SAA7283, for each data byte received. When the sub-address is equal to 04 (HEX), on reception of the next data byte, the sub-address will reset to 00 (HEX).
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
I2C-bus slave receiver register map Table 4 Slave receiver data byte SUB-ADDRESS 000 001 010 011 100 M1/M2 This bit selects either mono channel M1 or M2 to be the output on the left and right channel dependent on the transmitted control bits C1 and C2 indicating a mono transmission and the value of bit DMSEL (see Table 5). Power-on resets to logic 1. DMSEL DMSEL is the dual mono selection bit, for transmissions consisting of two independent mono signals. Selection is in conjunction with M1/M2 (see Table 5). Power on resets to logic 0. SSWIT1, SSWIT2 AND SSWIT3 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 7. Power-on resets to 010 with PORA pin HIGH, and to 011 with PORA pin LOW. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I2C-bus. See Table 6. Power-on resets to logic 0. MUTEDEF This defines the operation of the user definable MUTE pin or MUTE I2C-bus bit when it is pulled LOW externally or set LOW in the I2C-bus respectively. When this bit is HIGH, pulling the MUTE bit LOW will mute (set to zero) the digital data and switch the output to the FM input, depending on relevant control bits (see Table 8). When this bit is LOW, pulling the MUTE pin/I2C-bus bit LOW will only mute the digital data under the same conditions. Power-on resets to LOW. pin/I2C-bus D7 M1/M2 EMAX7 EMIN7 C4OV ASYS D6 DMSEL EMAX6 EMIN6 MUTE BG/I D5 SSWIT3 EMAX5 EMIN5 SILENCE NICLEV D4 SSWIT2 EMAX4 EMIN4 DAIE STLOCK AMDIS D3 SSWIT1 EMAX3 EMIN3 FM3 - D2 PORT2 EMAX2 EMIN2 FM2 - D1
SAA7283
D0 EMAX0 EMIN0 FM0 -
MUTEDEF AMDIS EMAX1 EMIN1 FM1 -
This bit enables and disables the automatic mute function. Power-on resets to enabled = LOW. EMAX7 TO EMAX0 This is the upper error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch IN. User definable, but power-on resets to 50 (HEX). EMIN7 TO EMIN0 This is the lower error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch OUT. User definable, but power-on resets to 14 (HEX). C4OV When set LOW this bit overrides the status of the transmitted C4-bit when muting. When this bit is HIGH muting takes place in accordance with EBU specification. Power-on resets to HIGH when the PORA pin is held LOW during power-up, and power-on resets to LOW when PORA is HIGH. MUTE This reflects the function of the MUTEB pin. When this bit is set LOW the external MUTEB pin is pulled LOW and the action is dependent on the MUTEDEF bit (see Table 8). Power-on resets to HIGH. SILENCE When set LOW this bit silences the outputs of the device by switching the input of the audio switching buffers to analog ground. When the PORM pin is held LOW at power-on reset the silence bit is initialized to zero. With PORM bit HIGH the silence bit is initialized HIGH.
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
DAIE When set HIGH this bit switches in the Digital Audio Interface output to the DOBM pin. When set LOW the DOBM output is 3-stated. Power-on resets to HIGH. FM3 TO FM0 These bits set the level of attenuation of the FM audio signal (see Table 9). Power-on resets 0000 = 0 dB attenuation. ASYS When this bit is HIGH it activates the automatic standard switch mode. When set LOW, the standard must be set by the BG/I bit. Power-on resets to HIGH. BG/I When this bit is HIGH it switches the DQPSK demodulator to system BGH and attenuates the digital audio level by Table 5 DMSEL 0 0 1 1 Table 7 SSWIT3 0 0 0 0 1 1 Note 1. Where X = don't care. Output as a function of M1/M2 and DMSEL M1/M2 0 1 0 1 FUNCTION selects DIGITAL; L = M2, R = M2 selects DIGITAL; L = M1, R = M1 selects DIGITAL; L = M2, R = M1 selects DIGITAL; L = M1, R = M2
SAA7283
4.6 dB (if NICLEV is set HIGH). When LOW, the DQPSK demodulator switches to system I (with no 4.6 dB attenuation). Power-on resets to HIGH. NICLEV When this bit is set LOW it overrides the 4.6 dB NICAM audio level compensation, irrespective of whether the device is in automatic or manual system mode. When set HIGH the 4.6 dB compensation level is applied in system BGH. Power-on resets to HIGH. STLOCK When STLOCK is set HIGH it will stop the automatic system switch after the device has achieved an INSYNC condition, should the demodulator lose lock at any time. This minimizes the re-acquisition time. When set LOW the device will be permitted to change system after an INSYNC condition has been reached. Power-on resets to LOW. Table 6 Port 2 control PIN OUTPUT STATE LOW HIGH
PORT2 0 1
SSWIT signal states and function SSWIT2 0 0 1 1 X(1) X SSWIT1 0 1 0 1 0 1 FUNCTION NICAM source de-emphasis switched out, no gain NICAM source de-emphasis switched in, no gain NICAM source de-emphasis switched in, +6 dB gain; power-on reset when PORA = HIGH NICAM source de-emphasis switched in, +12 dB gain; power-on reset when PORA = LOW external inputs switched in, no change to previous de-emphasis/gain setting FM inputs switched in, no change to previous de-emphasis/gain setting
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
Table 8 Action of pulling MUTE pin/I2C-bus bit LOW
SAA7283
TRANSMITTED C4 BIT (RSSF) 1 1 0 0 Note
OUTPUT ACTION(1) C4OV 1 or 0 1 or 0 1 0 TRANSMISSION MODE MUTEDEF = 1 stereo/mono/dual mono with L and R = M1 dual mono with M2 selected in either L or R all modes all modes mute digital data and switch to FM no action no action mute digital data and switch to FM MUTEDEF = 0 mute digital data only no action no action mute digital data only
1. With MUTE pin/i2C-bus bit pulled LOW. If user has manually selected FM or NICAM inputs, no switching will occur. Table 9 FM attenuation control FM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FM ATTENUATION (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 Not defined Not defined Not defined Slave transmitter format
The slave transmitter format is shown in Table 10. Table 10 Slave transmitter format START slave_addr ACK data_byte ACK n-bytes data_byte ACK STOP
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
Table 11 Explanation of Table 10 ITEM START Slave_addr X R ACK Data_byte ACK STOP I2C-bus start condition 101101XR logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 logic 1, I2C-bus read from slave transmitter I2C-bus acknowledge condition generated by slave receiver data byte transmitted from slave receiver master device negative acknowledge to indicate last byte I2C-bus stop condition DESCRIPTION
SAA7283
I2C slave transmitter register map The bus master can perform single-byte, two-byte, three-byte, four-byte or five-byte read in the order shown in Table 12. Table 12 Slave transmitter data byte BYTE STATUS BYTE 1 ERROR BYTE AD BYTE 0 AD BYTE 1 STATUS BYTE 2 PONRES When set HIGH this bit indicates that a power-on reset has occurred. It is cleared after the status byte has been read. S/M This bit gives the stereo or mono broadcast indication. Set HIGH indicates stereo transmission. D/S When HIGH this bit indicates a dual mono broadcast. VDSP When this bit is HIGH, it indicates that the digital data transmission is a sound source. When LOW the transmission is either data or undefined format. RSSF This bit reflects the state of the C4 bit in the NICAM transmission. When set LOW, the FM sound content does not match the digital transmission, and switching to FM by automatic mute or setting MUTE LOW is prevented (if C4OV = HIGH). 1996 Oct 24 16 CFC When LOW this bit indicates a configuration change at the C0 (16 frame) boundary. it is reset after reading the status byte. ERR7 TO ERR0 These bits indicate the number of errors occurring in the previous 128 ms period. AD7 TO AD0 These bits contain the eight least significant additional data bits. D7 ERR7 AD7 OVW C1 D6 ERR6 AD6 SAD C2 D5 D/S ERR5 AD5 0 C3 D4 VDSP ERR4 AD4 CI1 BG/I OS When HIGH this bit indicates that the device has both frame and C0 (16 frame) synchronization. AM When HIGH this bit indicates that the automatic mute function has switched from NICAM to FM. When LOW the automatic mute function has not activated a switch. D3 RSSF ERR3 AD3 CI2 0 OS ERR2 AD2 AD10 0 D2 AM ERR1 AD1 AD9 0 D1 D0 CFC ERR0 AD0 AD8 0
PONRES S/M
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
OVW This bit is set when new additional data bits are written to the I2C-bus without the previous bits being read. SAD This bit is set HIGH when new additional data is written into the I2C-bus, and cleared by the action of reading the data. CI1 AND CI2 These are the CI bits decoded by majority logic from the parity checks of the last ten samples in a frame. Indicator bits Table 13 is the truth table for the indicator bits. Table 13 Indicator bits functional truth table TRANSMISSION Stereo M1 + M2 M1 + data Transparent data Decoder unsynchronized (OS = logic 0) C1 0 0 1 1 C2 0 1 0 1 C3 0 0 0 0 S/M 1 0 0 0 0 0 D/S 0 1 0 0 0 0 AD10, AD9 AND AD8
SAA7283
These are the three most significant additional data bits. C1, C2 AND C3 These are the transmitted control bits, see Table 13. BG/I When set HIGH this bit indicates that the DQPSK demodulator is switched to system BGH. When LOW, indicates that DQPSK demodulator is switched to system I.
VDSP 1 1 1 0 0 0
OS 1 1 1 1 1 0
Any currently undefined combination of C1, C2 and C3
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Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
DIGITAL AUDIO INTERFACE IEC/EBU 958 Block structure The output is grouped into a block of 192 consecutive frames providing, for each channel the 192 channel status data bits. The start of a block is designated by a special sub-frame preamble. Frame structure Each frame is uniquely composed of two sub-frames. The rate of transmission of frames corresponds exactly to the source sampling frequency. In the 2-channel operation, samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to Channel 1 (left or `A' channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However the preamble is changed to preamble B once every 192 frames. This defines the block structure used to organize the channel status information. Sub-frames of Channel 2 (right or `B' channel in stereophonic operation and secondary channel in monophonic operation) always use preamble W. Sub-frame structure
SAA7283
Each frame is divided into 32 time-slots numbered 0 to 31. Time-slots 0 to 3 carry one of three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time-slots 4 to 27 carry the audio sample word in linear two's complement representation. The most significant bit is carried by time-slot 27. Time-slot 28 carries the validity flag associated with the audio sample word. This flag is set to logic 0 if the audio sample is reliable. If set to logic 1 then the sample is unreliable. Time-slot 29 carries one bit of the user data channel. In this application this is not used and so is set to logic 0. Time-slot 30 carries one bit of the channel status word associated with the audio channel transmitted in the same sub-frame. Time-slot 31 carries a parity bit such that time-slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros.
handbook, full pagewidth
M
channel 1
W
channel 2
B
channel 1 sub-frame
W
channel 2 M
channel 1 W
channel 2
sub-frame frame 1
MLB155
frame 191
frame 0 start of block
Fig.5 Frame format.
0
handbook, full pagewidth
34 sync preamble
MLB156
11 12
L S B
27 28
M S B
31
logical 0 bits
audio sample word
VUCP
validity flag user data = logic 0 channel status parity bit
Fig.6 Sub-frame structure.
1996 Oct 24
18
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
Channel coding Time-slots are encoded as biphase mark data. Each bit transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit being transmitted is logic 0, however it is different if the bit is logic 1 (see Table 14). Table 14 Channel coding PRECEDING STATE TRANSMITTED BIT 0 1 Preambles Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. A set of three preambles is used. These preambles are transmitted in the time allocated to four time-slots and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Depending on this state the preambles are as shown in Table 15. Table 16 Channel status codes BIT 0 1 2 3 and 4 5 6 and 7 8 to 5 16 to 19 20 to 23 24 to 27 28 and 29 30 to 191 CODE 0 0 1 00 11 0 00 00110001 0000 0000 1100 00 all 0s consumer sound data digital copy permitted indicates digital de-emphasis switched in indicates digital de-emphasis switched out - - category code source code (don't care) channel number (don't care) sampling frequency (32 kHz) clock accuracy (level II) - DESCRIPTION Channel status 0 1 Table 15 Preambles PRECEDING STATE PREAMBLE B M W 0
SAA7283
1
CHANNEL CODING 11101000 11100010 11100100 00010111 00011101 00011011
The preambles preceding each digital audio sample are used to indicate the beginning of a sample as follows: * Preamble B indicates the start of Channel A data and the beginning of a block * Preamble M indicates the start of Channel A data but not the beginning of a block * Preamble W indicates the start of Channel B data.
CHANNEL CODING 11 10 00 01
The channel status information is organized in 192-bit words. The first bit of each word is carried in the frame with Preamble B. The 192-bit word is organized into sections as shown in Table 16.
1996 Oct 24
19
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
LIMITING VALUES In accordance with the Absolute Maximum Rating Systems (IEC 134). SYMBOL VDDF1, VDDF2, VDDA VSSF1, VSSF2, VSSA VI(max) VO(max) IIOK IO(max) Tamb Tstg Vstat(HBM) Vstat(MM) Notes 1. All VDD and VSS connections must be made externally to the same power supply. PARAMETER supply voltage (all supplies) ground supply voltage maximum input voltage (any input) maximum output voltage DC input or output diode current output current (each output) ambient operating temperature storage temperature electrostatic handling Human Body Model Machine Model note 2 note 3 -2 000 -200 +2000 +200 CONDITIONS note 1 MIN. -0.3 VSSD - 0.5 0 0 - - -20 -55 MAX. +6.5
SAA7283
UNIT V V V V mA mA C C V V
VSSD + 0.5 VDD VDD 20 10 +70 +125
2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a 15 ns rise time. 3. Electrostatic handling is equivalent to discharging a 200 pF capacitor via a 0 series resistor with a 15 ns rise time. QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E". SYSTEM PERFORMANCE Bit Error Rate (BER) Table 17 shows input signal conditions which typically produce bit error rates of less than 10-3. Signal levels given in dB are related to the picture carrier reference level (0 dB) and based on the output level of the Philips range of sound IF down-converter ICs. All measurements at 2nd IF (intercarrier) frequencies (NICAM and FM only) using Philips Semiconductors TDSD3 Applications Board. Table 17 System performance INPUT SIGNAL CONDITIONS FM overmodulation [NICAM = -20 dB, FM = -10 dB (I)/-13 dB (B/G)] NICAM level with respect to picture carrier (FM deviation = 50 kHz) FM = -10 dB (I)/-13 dB (B/G) NICAM carrier-to-noise ratio (NICAM = -20 dB, FM deviation = 50 kHz) FM = -10 dB (I)/-13 dB (B/G) Acquisition time Maximum acquisition time = 1 s, measured from power-on reset to in-sync condition achieved. SYSTEM I 170 -44 9 SYSTEM BG 105 -43 10.5 UNIT kHz dB dB
1996 Oct 24
20
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Digital supplies (note 1) VDDD VSSD IDDD VDDA VSSA VSSDAC IDDA VDDF1 VSSF1 IDDF1 VDDF2 VSSF2 IDDF2 digital supply voltage digital ground supply voltage digital supply current 4.5 - - 5.0 0 15 5.5 - - PARAMETER CONDITIONS MIN. TYP.
SAA7283
MAX.
UNIT
V V mA
Audio supplies (note 1) audio supply voltage audio ground supply voltage DAC ground supply voltage audio supply current 4.5 - - - 5.0 0 0 19 5.5 - - - V V V mA
Demodulator supplies (note 1) 1st front-end supply voltage 1st front-end ground supply voltage 1st front-end supply current 2nd front-end supply voltage 2nd front-end ground supply voltage 2nd front-end supply current 4.5 - - 4.5 - - 5.0 0 46 5.0 0 125 5.5 - - 5.5 - - V V mA V V mA
Digital inputs DATAIN (TTL/CMOS COMPATIBLE INPUT LEVELS) VIL VIH ILI Ci VIL VIH Ri(pu) Ci VIL VIH Vhys ILI Ci LOW level input voltage HIGH level input voltage input leakage current input capacitance 0 2.0 -10 - 0 2.0 - - 0 3.0 - -10 - - - - - - - 50 - - - 0.05VDD - - 0.8 VDD +10 10 V V A pF
ADSEL, PORM AND PORA (TTL/CMOS COMPATIBLE INPUT LEVELS WITH INTERNAL PULL-UP) LOW level input voltage HIGH level input voltage input pull-up resistance input capacitance 0.8 VDD - 10 V V k pF
RESET AND SCL (CMOS/I2C-BUS INPUT LEVELS WITH SCHMITT TRIGGER) LOW level input voltage HIGH level input voltage hysteresis input leakage current input capacitance 1.5 VDD - +10 10 V V V A pF
1996 Oct 24
21
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL Digital input/output
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SDA (I2C-BUS LEVELS WITH SCHMITT TRIGGER/OPEN-DRAIN OUTPUT) VIL VIH Vhys ILI Ci VOL CL LOW level input voltage HIGH level input voltage hysteresis input leakage current input capacitance LOW level output voltage load capacitance active pull-up passive pull-up - - 0 2.0 - IOL = +3 mA IOH = -3 mA 0 2.4 - - - - - - - - - - 50 400 200 pF pF IOL = +3 mA 0 3.0 0.05VDD -10 - 0 - - - - - - 1.5 VDD - +10 10 0.4 V V V A pF V
MUTE (TTL/CMOS COMPATIBLE INPUT LEVELS/OPEN-DRAIN OUTPUT WITH INTERNAL PULL-UP) VIL VIH Ci VOL VOH Ci Zi LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage HIGH level output voltage load capacitance with active pull-up input impedance 0.8 VDD 10 0.4 VDD 50 - V V pF V V pF k
Digital outputs PORT2, PCLK AND DATAOUT (PUSH-PULL OUTPUT) VOL VOH CL VOL VOH CL ILI LOW level output voltage HIGH level output voltage load capacitance IOL = +2 mA IOH = -2 mA 0 2.4 - IOL = +2 mA IOH = -2 mA VI = 0 to VDD 0 2.4 - -10 - - - - - - - 0.4 VDD 50 V V pF
DOBM (3-STATE PUSH-PULL OUTPUT) LOW level output voltage HIGH level output voltage load capacitance 3-state leakage current 0.4 VDD 50 +10 V V pF A
ANALOG SECTION (measured at VDD = 5 V; Tamb = 25 C) Demodulator analog references VRCF OUTPUT Vo Ci VROF OUTPUT Vo Ci output signal voltage input capacitance defined by VRCF - - 0.5VDDF2 - - 10 V pF output signal voltage input capacitance supply dependent - - 0.5VDDF2 - - 10 V pF
1996 Oct 24
22
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL IREF OUTPUT Vo Ci Isink
PARAMETER
CONDITIONS - - with external 10 k resistor from pin to VSSF2 -
MIN.
TYP. 0.5VDDF2 - - 250
MAX.
UNIT
output signal voltage input capacitance output sink current
defined by VRCF
V pF A
10 -
Signal path analog inputs DQPSK AND MIXREF Ri ViDQPSK(rms) ViDR ViCUM(rms) Ci input resistance NICAM input signal voltage Vnom (RMS value) AGC range cumulative input signal voltage (RMS value) input capacitance with respect to ViDQPSK note 2 - - +8.5 -25 - - 12.5 43 +10 -30 - - - - - - 464 10 k mV dB dB mV pF
Baseband outputs CEYE AND SEYE Vo(p-p) eye pattern output signal voltage (peak-to-peak value) in-lock; note 3; system I in-lock; note 3; system B/G VI/Q channel matching 20log10 (VCEYE/VSEYE) defined by VRCF - - -2 1.25 1.79 0 - - +2 V V dB
COFF AND SOFF VO offset compensator DC output voltage - 0.5VDDF2 - V
Baseband filters SYSTEM I Afo FMr FMomr CCr pass band cut-off attenuation FM rejection FM rejection (overmodulated FM) colour-carrier rejection fi = 6552 MHz + 182 kHz fi = 6.0 MHz 50 kHz fi = 6.0 MHz 80 kHz fi = 4.43 MHz 1.9 - 45 - 3.1 65 50 78 4.6 - - - dB dB dB dB
1996 Oct 24
23
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL SYSTEM BGH Afo FMr AMr (SECAM) FMomr CCr
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
pass band cut-off attenuation FM rejection AM rejection (for SECAM L system) FM rejection (overmodulated FM) colour-carrier rejection
fi = 5850 MHz + 182 kHz fi = 5.5 MHz 50 kHz fi = 6.5 MHz fi = 5.5 MHz 80 kHz fi = 4.43 MHz
1.7 - - 25 -
3.1 50 56 30 73
4.5 - - - -
dB dB dB dB dB
Baseband demodulator output REMO Vo Kp fp offset fn output voltage limits carrier loop-phase detector gain carrier loop pull-in frequency carrier loop-phase detector offset carrier loop bandwidth (natural frequency) phase shift = 45 system I system B/G 0.2 - - 4 -4 2 - 1.2 0.9 - 0 - VDD - 0.5 V - - - +4 5 V/rad V/rad kHz deg kHz
Baseband remodulator filter feedback REMVE Vo Isource Isink ILI ffstep carrier loop filter virtual earth voltage defined by VRCF output source current output sink current 3-state leakage current fine frequency calibration step - - - -0.25 0.8 0.5VDDF2 - 15 15 0 2 - - +0.25 8 V A A A kHz
Fine frequency calibration current (on to REMVE node)
Voltage controlled oscillator VCONT Vi Ci input signal voltage input capacitance 0.5 - - - VDD - 0.5 V 10 pF
1996 Oct 24
24
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL
PARAMETER
CONDITIONS
MIN. fSYS - 75 fSYS - 4 -139 -191 -50 - - -
TYP.
MAX.
UNIT
VCO (MEASURED AT VCLK PIN) fVCO VCO frequency after DAC calibration VCO frequency after fine frequency calibration KVCO DACSTEP ItoQ j VCO slope VCO calibrating DAC step size in-phase to quadrature phase accuracy VCO phase jitter note 4 fSYS = 6552 MHz (system I) or fSYS = 5.85 MHz (system BGH) system I system B/G fSYS + 75 kHz fSYS + 4 -232 -319 +50 - 8.1 kHz kHz/V kHz/V kHz deg ns
-186 -255 +30 90 -
-
Clock recovery loop and crystal oscillator XTAL Ci Vbias OSC Vosc(p-p) Vbias Gv Co fi CL C1 C0 S Rr RDLD Xa Trange Xj Xd ILI gm oscillator voltage amplitude (peak to peak value) DC bias voltage small signal voltage gain output capacitance - - - - - - 21 - determined by CL, C1 and C0 -26.25 - - - -20 - across Trange 0.5 VCLKLPF VDD - 0.5; note 5 0.5 VCLKLPF VDD - 0.5; note 5 - -5 57 1.4 2.33 1.0 - 8.192 15 - - - - - - +25 - - 0 63.5 - - - 10 - - - 5 - 40 120 5 +70 30 30 +5 70 V V V/V pF input capacitance DC bias voltage - - - 3.63 10 - pF V
CRYSTAL SPECIFICATION (FUNDAMENTAL MODE) crystal input frequency load capacitance series capacitance parallel capacitance pulling sensitivity resonance resistance resonance resistance; drive level dependency ageing temperature range adjustment tolerance drift 3-state leakage current at 2 phase shift phase comparator transconductance MHz pF fF pF 10-6/pF 10-6/year C 10-6 10-6 A A/rad
CLOCK RECOVERY LOOP CURRENT SOURCE (CLKLPF)
1996 Oct 24
25
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL Analog references VRCA OUTPUT Vo Ci VROA OUTPUT Vo Ci Digital filter fs PR SBA
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
output signal voltage input capacitance
supply dependent
- -
0.5VDDA - 0.5VDDA -
- 10 - 10 - 0.01 - 0.09
V pF
output signal voltage input capacitance
defined by VRCA
- - -
V pF
output sample frequency pass band ripple stop band attenuation at 0 Hz to 15 kHz at f 17 kHz
128 - - -
kHz dB dB
- 30 -
Digital de-emphasis DEV deviation from ideal dB
FM audio inputs FML AND FMR (SELECTED VIA I2C-BUS CONTROL) Zi input impedance 0 dB FM attenuation set -12 dB FM attenuation set G Ga Vain(rms) S/N THD output gain output gain accuracy input voltage level (RMS value) signal-to-noise ratio total harmonic distortion programmable in 1 dB steps - - - -0.5 - 90 - 40 160 0 to 12 0 - 95 -85 - - - +0.5 1.1 - -70 k k dB dB V dB dB
EXT audio input EXTL AND EXTR (SELECTED VIA I2C-BUS CONTROL) Zi G Ga Vain(rms) S/N THD input impedance output gain output gain accuracy input voltage level (RMS value) signal-to-noise ratio total harmonic distortion - - - - 90 - 40 0 0 - 95 -85 - - - 1.1 - -70 k dB dB V dB dB
NICAM internal DAC (selected via I2C-bus control) Vo(rms) THD+N DIGS AUDIOS 1996 Oct 24 NICAM output voltage level (RMS value) total harmonic distortion plus noise digital silence level audio silence level 0 dB; VROA = 2.5 V 0.94 notes 6 and 7 MUTE on SILENCE on = 0 26 - - -80 1 -80 -80 - 1.06 -75 - - V dB dB dB
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
SYMBOL Audio outputs OPL AND OPR CL RL CHM PSRR
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
output load capacitance output load resistance channel matching power supply rejection ratio 0 dB, 1 kHz
- 3 -0.5 -
- - 0 40
300 - +0.5 -
pF k dB dB
Timing (all timing values refer to VIH and VIL levels) DATAIN WITH RESPECT TO PCLK (see Fig.9) tSU;DAT tHD;DAT fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Notes 1. It is assumed that all supplies are externally connected at the same source, and consequently that maximum and minimum values apply simultaneously to each supply. 2. Cumulative input level based on FM at 0 dB and NICAM at -10 dB with respect to picture carrier. 3. The signal amplitude present at the SEYE and CEYE pins depends on whether the demodulator is in or out-of-lock. When out-of-lock, the signal at the pins is 2 times the in-lock situation. 4. VCO jitter is measured in System I over 100 cycles of the VCO clock. 5. With 10 k resistor from IREF to VSSF2. 6. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to compansion, the quantization noise is never lower than -62 dB with respect to the input level. 7. Measured with a -30 dB, 1 kHz NICAM 728 input signal. 8. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. 9. If a fast I2C-bus device is used in an up to 100 kbit/s I2C-bus system, then the requirement tSU;DAT 250 ns is always fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL signal, then data to SDA must be asserted (tRD(max) + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL signal is released to be compatible with the up to 100 kbit/s I2C-bus specification. data set-up time data hold time 100 250 - - - - - - - - - - - - - - - 400 - - - - - - - 300 300 - ns ns
SDA WITH RESPECT TO SCL(see Fig.10) SCL clock frequency bus free time START code hold time SCL clock LOW time SCL clock HIGH time START code set-up time data hold time data set-up time SDA and SCL rise time SDA and SCL fall time STOP code set-up time note 8 note 9 0 1300 600 1300 600 600 0 100 50 50 600 kHz ns ns ns ns ns ns ns ns ns ns
1996 Oct 24
27
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
handbook, full pagewidth
supply 2.2 2.2 22 10
100 nF
47 F
100 nF V DDF1
47 F V DDF2
100 nF VDDD
100 nF VDDA
SAA7283
MGB466
Fig.7 VDD external circuitry.
1996 Oct 24
28
1996 Oct 24
SAW FILTER VISION IF DEMODULATOR (TDA9803) COMPOSITE VIDEO 8.192 MHz DOBM I 2 C-BUS 2 39.5 MHz (I) 38.9 MHz (BG) - 6 dB DAI 6 MHz (I) 5.5 MHz (BG) STEREO BITSTREAM DAC AND SWITCHES NICAM DECODER I 2C AUDIO OUTPUTS LEFT
Philips Semiconductors
RF handbook, full pagewidth INPUT
TUNER
32.95 33.5 33.05 33.4
39.5 MHz (I) 38.9 MHz (BG)
Terrestrial Digital Sound Decoder (TDSD3)
29
SOUND IF DEMODULATOR TDA3867 DQPSK DEMODULATOR
RIGHT
SAA7283
EXTERNAL AUDIO INPUTS ANALOG FM SOUND
MGB467
Preliminary specification
SAA7283
Fig.8 System block diagram showing SAA7283.
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
handbook, full pagewidth
PCLK
DATA
MLB158
t SU;DAT
t HD;DAT
Fig.9 Data output timing.
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL t HIGH t SU;DAT
t HD;STA
tr
t HD;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.10 I2C-bus timing.
1996 Oct 24
30
390 pF 100 10 pF VDDF1 VSSF1 10 F VSSF2 VSSF1 VSSF1 47 F 10 k 33 k 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 FMR EXTR n.c. V RCA n.c. 2 1 47 F n.c. 10 k 1 M VSSA 10 digital audio interface VSSD VDDA 100 nF VSSA 100 nF VSSA 47 F VSSA 68 pF 100 nF VSSA 47 VSSA F VSSA 220 nF 220 nF FMR EXTR 220 nF VSSA 1.8 k 47 nF VSSA 1 M 68 pF audio left 10 F 10 F 32 31 30 29 28 27 26 25 24 23 22 21 20 n.c. n.c. VCLK SOFF n.c. CEYE COFF SEYE VSSF1 100 nF VSSF1 100 nF 47 F
2.2
DQPSK input 1 k
VSSF1
DQPSK MIXREF
34 PKDET VROF REMO REMVE PORA PORM EXTL FML OPL I REF VRCF VDDF2 V SSF2 TEST CLKLPF XTAL n.c. n.c. V SSDAC VROA n.c. n.c. OPR n.c. 35 10 k 36 37 100 nF 1 F 39 40 41 42 100 pF 43 OSC VSSX DATAIN DATAOUT PCLK VSSD VDDD RESET n.c. SDA PORT2 n.c. SCL ADSEL MUTE n.c. DOBM V DDA V SSA 44 45 46 47 100 nF 48 49 50 51 100 pF 38
VDDF2
2.2
220 pF
100 nF
10 F
100 nF
10 F
VSSF2
V DDF1
n.c.
VCONT
Preliminary specification
SAA7283
Fig.11 Application diagram for QFP64.
handbook, full pagewidth
1996 Oct 24
33 n.c.
VDD (5 V)
VSSF1
Philips Semiconductors
supply connector
APPLICATION INFORMATION
VSS
Terrestrial Digital Sound Decoder (TDSD3)
31
SAA7283
22 52 53 54 55 56 57 58 59 60 61 62 63 64 VDDD SCL SDA I 2 C bus connector VSSD
220 nF EXTL FML
330 nF
22 k
8.192 MHz
22 nF
1 M
VSSF2
6.8 H
BB405
VSSF2
VSSD
VDDD
680 k
BAW62
470 nF
audio right
VSSD
MGB468
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SAA7283
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1996 Oct 24
32
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SAA7283
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 wM D HD ZD 19
20
e
bp
vMA B vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Oct 24
33
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1996 Oct 24 34
SAA7283
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Preliminary specification
Terrestrial Digital Sound Decoder (TDSD3)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7283
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 24
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp36
Date of release: 1996 Oct 24
Document order number:
9397 750 01421

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